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Cadence Design Systems: Physical Design Flow Expert

Cadence Design Systems

This is a Full-time position in Montreal, QC posted February 21, 2021.

We are looking for a CAD/PDK engineer to work with the digital layout flow development team.

The engineer would help to enable advanced technology nodes, support ongoing IP programs, maintain and improve Cadence internal physical design flow.The candidate must be willing to work in our Montreal office and have a valid work permit, permanent residency or citizenship of Canada.Job ResponsibilitiesAutomate tasks, test enhancements and bug fixes, run benchmarksDevelop and maintain technology setup: PDK inputs, standard cells, floorplan procedures, signoff checks setup, tool settingsRun test case designs through synthesis, place-and-route, static timing closure, power analysis, physical verification (DRC/LVS)Provide support to ongoing projects (questions, hands-on debugging).

The candidate should be able to communicate clearly in English.Follow tool new features and known issuesParticipate in documentation and quality checks in prevision of new flow releasesPossible travel opportunities to attend or give trainingMinimum RequirementsBachelor’s degree in Electrical/Electronic Engineering and at least four (4) years of relevant experience.

Or, a Master of Science in Electrical Engineering and at least two (2) years of relevant experienceExperience with ASIC RTL to GDS flow, at block or chip levelDeep knowledge about industry standard and practices in Physical Design, including synthesis, floor-planning, power grid implementation, clock specifications, placement & routing, and signoff verification such as STA, IR drop, EM, DRC, LVS, etc.Deep Understanding of scripting languages such as TclExcellent communication skillsKnowledge of the following Cadence tools (or industry equivalent): Innovus, Tempus, Voltus, PVS/Pegasus, Conformal